CMP is a well known technique for processing films and layers, in particular metal films and layers, during integrated circuit fabrication processes, as evidenced by the following representative U.S. Pat. No. 6,179,690, “Substrate polishing apparatus”; U.S. Pat. No. 6,162,728, “Method to optimize copper chemical-mechanical polishing in copper damascene interconnect process for integrated circuit applications”; U.S. Pat. No. 6,117,777, “Chemical mechanical polish (CMP) endpoint detection by colorimetry”; U.S. Pat. No. 5,976,982, “Methods for protecting device components from chemical mechanical polish induced defects”; U.S. Pat. No. 5,863,307, “Method and slurry composition for chemical-mechanical polish (CMP) planarizing of copper containing conductor layers”; U.S. Pat. No. 5,780,358, “Method for chemical-mechanical polish (CMP) planarizing of copper containing conductor layers”; and U.S. Pat. No. 5,674,783, “Method for improving the chemical-mechanical polish (CMP) uniformity of insulator layers”.
It has been observed that surface pitting occurs during the CMP stage of an integrated circuit manufacturing process when using, for example, copper metal films. The presence of these surface pits is undesirable, and is considered a failure mechanism. It is believed that the presence of the pits may cause increased contact resistance and electromigration, as well as Cu residual issues, which can adversely affect device functioning.
At present, the mechanism that causes the pitting is not well understood. The pit failures could originate during the deposition of the copper via an electro-chemical deposition (ECD) process (i.e., plating), or the pit failures could originate during the CMP process itself. If the latter is true then the pitting mechanism may be found to result from overly aggressive chemistry, e.g., the acidic component of the CMP slurry is made too strong. The pits are generally found to have irregular shapes and sizes, typically less than about 30 μm2, and a depth of about 10 nm to about 30 nm.
Whatever their cause, the pits are not readily detectable by in-line inspection tools (e.g., optical microscope, AIT2 and CD-SEM). This, obviously, presents a problem to the manufacturers of integrated circuits who employ a CMP process.